1. Field of the Invention
This invention relates generally to semiconductors, and more particularly, to a semiconductor device having a semiconductor memory.
2. Description of the Related Art
Some semiconductor memory devices compare data in a reference cell and data in a regular cell to read the data from the regular cell. Referring to FIG. 1, a flash memory will be described as an example of such a semiconductor memory device.
FIG. 1 is a block diagram of memory cells and periphery circuitry therefor in accordance with a conventional flash memory. A regular sector 10 includes regular cells 16. Regular cells 16a, 16b, and 16c of the regular cells 16 are respectively connected by word lines 14a, 14b, and 14c and bit lines 18. The word lines 14a, 14b, and 14c are connected to a word driver 12. The bit lines 18 are connected to a sensing amplifier 30. A reference cell 26 is disposed in a reference sector 20. The reference cell 26 is connected by a word line 24 and a connection line 32. The word line 24 is connected to a reference word driver 22 and the connection line 32 is connected to the sensing amplifier 30.
Data reading is described with the regular cell 16a serving as an example. The word driver 12 selects the word line 14a connected to the regular cell 16a. The bit line 18 connected to the regular cell 16a is then selected. The sensing amplifier 30 compares the threshold voltage of the regular cell 16a and that of the reference cell 26. This accomplishes reading of the regular cell 16a to learn whether the regular cell 16a represents “0” or “11”.
Each of the regular cells 16 has a “word line distance” which is a distance along each of word lines 14 from the word driver 12 to each of the regular cells 16. Similarly, each of the reference cells 26 has a “reference word line distance” which is a distance along each of the reference word lines from the reference word driver 22 to each of the reference cells 26.
As an example of a semiconductor memory device having multiple reference cells, Japanese Patent Application Publication 9-270195 discloses a semiconductor device that includes multiple reference cells having different resistances and capacitances in their wirings to the sensing amplifier. Japanese Patent Application Publication 10-11985 discloses a semiconductor device having a reference cell arranged close to the regular cell.
In accordance with conventional techniques, the word driver 12 is located on one side of the regular sector 10 in order to reduce a chip area. Such reduced chip area increases the number of the regular cells 16 connected to each of the word lines 14. Accordingly, when the chip area is reduced, the word line 14 becomes longer. This causes several shortcomings. Referring to FIG. 1 again, the regular cells 16a, 16b, and, 16c have different word line distances La, Lb, and, Lc, respectively. As the word line 14 lengthens, differences become greater between the word line distances La, Lb, and, Lc. This increases the differences in the resistances and capacitances of the word lines 14 applied to the regular cells 16. Consequently, this will cause different delay times in outputs to the sensing amplifier 30 from the regular cells 16a, 16b, and 16c. 
For example, when there the delay time of the output from the reference cell 26 to the sensing amplifier 30 is configured almost equal to that of the delay time from the regular cell 16b to the sensing amplifier 30, the delay time from the regular cell 16a to the sensing amplifier 30 is shorter than the delay time from the reference cell 26 to the sensing amplifier 30. On the other hand, the delay time from the regular cell 16c to the sensing amplifier 30 is longer than the delay time from the reference cell 26 to the sensing amplifier 30. If the delay time varies depending on the regular cells 16 in this manner, there will be no operation margin in the sensing amplifier 30 and the sensing amplifier 30 will operate unstably. In order to prevent the afore-described shortcomings, a limitation is set on the number of regular cells connected to the word line 14. Alternatively, the operating time of the sensing amplifier 30 must necessarily be lengthened. In other words, it is difficult to realize both reduction of the chip area and speeding up of the sensing operation.